1. Field of the Invention
This invention relates to a multi-chips semiconductor package and fabrication method, and particularly to a semiconductor package and fabrication method that includes two or more chips with same or different function overlapping with one another in the package, one of the chips using a lead frame as connection interface with external circuit while another chip using solder balls as connection interface with external circuit.
2. Description of the Prior Art
In the semiconductor industry, one of the research subjects almost all companies have tried to focus is to put as many logic circuits as possible in a smaller semiconductor package to reduce cost. One approach for this issue is to shrink the circuit design to a smaller width. Another approach is to cram two or more chips in a package so that cost may be reduced while circuit density may be increased at similar package size.
FIG. 1 shows one of conventional multi-chips semiconductor package examples which uses Lead On Chip (LOC) technology to connect two chips 1a and 1b respectively with two lead frames 3a and 3b through two-sided adhesive tapes 2a and 2b, then bond the chips 1a and 1b respectively to the mating leads of the lead frames 3a and 3b via bonding wires 4a and 4b. The leads of the lead frame 3a then connect with the leads 6 of the lead frame 3b. The whole assembly is filled and wrapped with molding epoxy 5 to form a complete semiconductor package component. In this example, the leads 6 of the lead frame 3b are used as connection interface between the circuits on the chips 1a and 1b and external circuits. When circuit chip number is doubled in the package the number of leads 6 shall also be doubled. Hence the length of t package component has to increase to accommodate more leads need In recent years, lead number of a single chip package component (such as 4 MB DRAM IC) has increased from twenty or thirty leads to forty-two or fifty leads. As a lead has a fixed width, the length of the IC component has increased significantly. Adopting the technique set forth above, the lead number of a package component could easily reach eighty leads or even one hundred leads. The package size becomes too big and not practical.
FIG. 2 shows another conventional multi-chips semiconductor package example. It employs Ball Grid Array (BGA) technology which uses EPOXY to adhere two chips 7a and 7b together, and then mounts the chips on a substrate 8. The chips 7a and 7b are bonded respectively with mating bonding pads located in the substrate 8 via gold wires 9a and 9b. The bonding pads connect with an array of solder balls 10 located on the bottom surface of the substrate 8. Through such a structure and package, the circuitry in the chips 7a and 7b may connect with external circuitry via the solder balls 10. One of the drawbacks of the BGA package is the large size of the substrate 8 resulting from solder ball array formation. Another problem is that the length of gold wire 9a is almost twice that of the gold wire 9b. The bonding of lengthy gold wire is difficult and may cause many other problems such as broken wire due to external force or overheating resulting from high resistance of lengthy wire. Moreover the size of the chip 7a on the top must be smaller than the size of the chip 7b at the bottom. Same size or same specification of chips cannot be used in this package. High density of gold wires 9a and 9b in the package is another source of the defect when molding with EPOXY. The gold wires are prone to break in the molding process and resulting in low yield of production. Both LOC and BGA methods have their practical limitation for multi-chips package application because of aforesaid problems.